Scholarly open access journals, Peer-reviewed, and Refereed Journals, Impact factor 8.14 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool) , Multidisciplinary, Monthly, Indexing in all major database & Metadata, Citation Generator, Digital Object Identifier(DOI)
The increasing demand for energy-efficient and secure hardware in modern computing platforms has spotlighted a critical challenge in ASIC design: balancing low power consumption with robust security verification. This review systematically explores recent research at this intersection, summarizing over a decade of innovation in power-aware security analysis, co-verification frameworks, and practical implementations. We present a conceptual block diagram, a proposed theoretical model, and experimental evidence quantifying trade-offs using side-channel vulnerability metrics, verification coverage, and post-silicon behavior. Future directions including AI-based optimizers, lifecycle-aware security, and post-quantum logic are discussed. The goal is to equip ASIC designers and verification engineers with actionable insights and frameworks to optimize both power and trust in next-generation chips.
"Low Power and Security Trade-offs in ASIC Verification: A Practical Approach", International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2455-2631, Vol.10, Issue 7, page no.b476-b481, July-2025, Available :http://www.ijrti.org/papers/IJRTI2507169.pdf
Downloads:
000404
ISSN:
2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator