Scholarly open access journals, Peer-reviewed, and Refereed Journals, Impact factor 8.14 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool) , Multidisciplinary, Monthly, Indexing in all major database & Metadata, Citation Generator, Digital Object Identifier(DOI)
Devices with low power consumption are essential in the present electronic era of circuit shrinking. Power consumption is one of the difficult variables that has an impact on the design of small devices and high-performance ICs. The typical SRAM cell designs are power-hungry and unimpressive in this new era of quick mobile computing. The power consumption of low power SRAM cell designs has been examined in this study. Conventional 6T SRAM cell, Gated VDD and Stacking based SRAM cell is designed using PMOS access transistors. The design is implemented and analyzed for static power consumption at 45nm technology in Cadence Virtuoso. Gated VDD using PMOS access transistors shows reduced static power when compared to above SRAM cells.
Keywords:
Cite Article:
"Design and analysis of SRAM cell with PMOS access transistor", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.7, Issue 10, page no.661 - 665, October-2022, Available :http://www.ijrti.org/papers/IJRTI2210090.pdf
Downloads:
000205041
ISSN:
2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator