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International Journal for Research Trends and Innovation
International Peer Reviewed & Refereed Journals, Open Access Journal
ISSN Approved Journal No: 2456-3315 | Impact factor: 8.14 | ESTD Year: 2016
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Issue: April 2026
Volume 11 | Issue 4
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Impact Factor : 8.14
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| Paper Title: | Low-Power 4×4 Signed Multiplier Design Using Pass-Transistor Logic at 16nm PTM |
| Authors Name: | K V Surya Vineeth , Ch.Vinay , D.Vinay Kumar , C V P Supradeepthi |
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IJRTI_211436
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| Published Paper Id: | IJRTI2604194 |
| Published In: | Volume 11 Issue 4, April-2026 |
| DOI: | |
| Abstract: | —In contemporary digital logic, multipliers are essential compute units that have a direct influence on power, performance, and area metrics in embedded systems, machine learning accelerators, and digital signal processors. This work offers a thorough approach to constructing a 4x4 signed multiplier with low power consumption and fast speed at the 16nm technology node utilising Pass-Transistor Logic (PTL). XOR, AND, half adder, and full adder are examples of custom transistor-level PTL gates that are tuned for fewer transistors, better signal integrity, and lower dynamic power. The solution bridges device level simulation with automated digital backend implementation by combining a standard array architecture with thorough signed operation verification and proving physical manufacturability using an open-source RTL-to-GDSII pipeline. At bigger technology nodes, experimental results demonstrate notable gains over earlier PTL implementations: compared to reference designs at 28nm, power consumption decreased by about 55%, propagation latency by 40%, and silicon area by 18%. Benchmarking verifies that PTL designs are feasible for modern VLSI systems and attests to their robustness and functional accuracy over all signed input combinations. In addition to laying the groundwork for future research on higher-order multipliers, hybrid logic integration, and specialised application targets, the method creates scalable, energy-efficient arithmetic build blocks. Index Terms |
| Keywords: | Pass-Transistor Logic (PTL), Low Power, Signed Multiplier, VLSI Design, RTL-to-GDSII Flow, Cadence Virtuoso. |
| Cite Article: | "Low-Power 4×4 Signed Multiplier Design Using Pass-Transistor Logic at 16nm PTM", International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2456-3315, Vol.11, Issue 4, page no.b430-b438, April-2026, Available :http://www.ijrti.org/papers/IJRTI2604194.pdf |
| Downloads: | 00041 |
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2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016 An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator |
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Published Paper ID: IJRTI2604194
Registration ID:211436
Published In: Volume 11 Issue 4, April-2026
DOI (Digital Object Identifier):
Page No: b430-b438 Country: hyderabad, telangana , India Research Area: Electronics & Communication Engg. Publisher : IJ Publication Published Paper URL : https://www.ijrti.org/viewpaperforall?paper=IJRTI2604194 Published Paper PDF: https://www.ijrti.org/papers/IJRTI2604194 |
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ISSN: 2456-3315
Impact Factor: 8.14 and ISSN APPROVED,
Journal Starting Year (ESTD) : 2016
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