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International Journal for Research Trends and Innovation
International Peer Reviewed & Refereed Journals, Open Access Journal
ISSN Approved Journal No: 2456-3315 | Impact factor: 8.14 | ESTD Year: 2016
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Issue: April 2026
Volume 11 | Issue 4
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Impact Factor : 8.14
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| Paper Title: | Efficient Sequential Circuit Design and Implementation Using 7nm PTM |
| Authors Name: | M.V.Sai Dharahas , K.Vilson , Y.Stephen , C V P Supradeepthi |
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IJRTI_211435
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| Published Paper Id: | IJRTI2604161 |
| Published In: | Volume 11 Issue 4, April-2026 |
| DOI: | |
| Abstract: | The design and implementation of sequential circuits such as D Flip Flop and Johnson Counter at the 7nm technology node are more challenging due to the strict performance, power, and area constraints inherent in advanced semiconductor scaling. Using an open-source RTL to GDS-II design pipeline and the 7nm Predictive Technology Model (PTM), this work provides a thorough examination of the methods and optimization techniques needed for reliable nanoscale digital systems. The process, which includes high level synthesis, logic optimization, physical design, and verification, shows how notional RTL is converted into silicon layouts that can be manufactured using open-source tools like ASAP7, Yosys, and Open ROAD, as well as predictive process design kits. Targeted solutions are provided for important issues such temporal closure, signal integrity, and leakage power, emphasizing the function of contemporary Electronic Design Automation (EDA) tools in enabling accurate validation and smooth stage integration. Performance measures evaluated experimentally demonstrate how well the 7nm PTM works to create dense, fast, and energy-efficient sequential circuits. For researchers and engineers aiming to create dependable, power-efficient digital circuit designs at the vanguard of semiconductor technology, such findings highlight the vital significance of cooperative, open-source approaches for cutting-edge VLSI innovation. |
| Keywords: | 7nm Predictive Technology Model (PTM), Sequential Circuits, RTL to GDS-II Flow,ASAP7, Yosys, Open ROAD, FinFET, VLSI Design, Semiconductor Technology Nodes. |
| Cite Article: | "Efficient Sequential Circuit Design and Implementation Using 7nm PTM", International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2456-3315, Vol.11, Issue 4, page no.b168-b175, April-2026, Available :http://www.ijrti.org/papers/IJRTI2604161.pdf |
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2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016 An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator |
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Published Paper ID: IJRTI2604161
Registration ID:211435
Published In: Volume 11 Issue 4, April-2026
DOI (Digital Object Identifier):
Page No: b168-b175 Country: Hyderabad, Telangana, India Research Area: Electronics & Communication Engg. Publisher : IJ Publication Published Paper URL : https://www.ijrti.org/viewpaperforall?paper=IJRTI2604161 Published Paper PDF: https://www.ijrti.org/papers/IJRTI2604161 |
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ISSN: 2456-3315
Impact Factor: 8.14 and ISSN APPROVED,
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