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International Journal for Research Trends and Innovation
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ISSN Approved Journal No: 2456-3315 | Impact factor: 8.14 | ESTD Year: 2016
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Issue: April 2026
Volume 11 | Issue 4
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Impact Factor : 8.14
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| Paper Title: | Design and Performance Analysis of Multi-Digit BCD Adder Using Brent–Kung Architecture |
| Authors Name: | K. Rojamani , S. Praneeth Sai , B. Hanumantha Rao , Y. V. V. S. N. Manikanta |
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| Author Reg. ID: |
IJRTI_211183
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| Published Paper Id: | IJRTI2604080 |
| Published In: | Volume 11 Issue 4, April-2026 |
| DOI: | https://doi.org/10.56975/ijrti.v11i4.211183 |
| Abstract: | The design of high-speed and power-efficient arithmetic units is a critical requirement in modern VLSI systems, especially for applications requiring accurate decimal computations such as financial processing and digital signal processing. This paper presents the design and performance analysis of a multi-digit Binary Coded Decimal (BCD) adder using the Brent–Kung Adder (BKA) architecture. The proposed design utilizes a parallel prefix structure to optimize carry propagation, thereby reducing logic depth and improving overall performance. The architecture is implemented using Verilog HDL and evaluated for different digit configurations. A comparative analysis is carried out with the conventional Carry Lookahead Adder (CLA) based BCD adder in terms of delay and power consumption. The results demonstrate that the proposed BKA-based BCD adder achieves a significant reduction in propagation delay and power usage. Specifically, delay is reduced by approximately 32% for lower digit configurations and around 22% for higher digit designs. Similarly, power consumption is reduced by up to 10% compared to the existing CLA-based approach. These improvements are mainly attributed to the efficient carry computation mechanism and reduced logic complexity of the Brent–Kung architecture. Furthermore, the proposed design exhibits better scalability with increasing digit size, making it highly suitable for high-performance and low-power VLSI applications. |
| Keywords: | VLSI, BCD Adder, Brent Kung Adder, Carry Lookahead, Verilog HDL |
| Cite Article: | "Design and Performance Analysis of Multi-Digit BCD Adder Using Brent–Kung Architecture", International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2456-3315, Vol.11, Issue 4, page no.a580-a586, April-2026, Available :http://www.ijrti.org/papers/IJRTI2604080.pdf |
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2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016 An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator |
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Published Paper ID: IJRTI2604080
Registration ID:211183
Published In: Volume 11 Issue 4, April-2026
DOI (Digital Object Identifier): https://doi.org/10.56975/ijrti.v11i4.211183
Page No: a580-a586 Country: Machilipatnam,Krishna District, Andhra Pradesh, India Research Area: Engineering Publisher : IJ Publication Published Paper URL : https://www.ijrti.org/viewpaperforall?paper=IJRTI2604080 Published Paper PDF: https://www.ijrti.org/papers/IJRTI2604080 |
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ISSN: 2456-3315
Impact Factor: 8.14 and ISSN APPROVED,
Journal Starting Year (ESTD) : 2016
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