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International Journal for Research Trends and Innovation
International Peer Reviewed & Refereed Journals, Open Access Journal
ISSN Approved Journal No: 2456-3315 | Impact factor: 8.14 | ESTD Year: 2016
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Issue: April 2026
Volume 11 | Issue 4
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Impact Factor : 8.14
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| Paper Title: | Timing and Power Optimization in Chiplet-Based SoCs with Heterogeneous Interconnects |
| Authors Name: | Phaneendra Chainulu Sri Adibhatla |
| Download E-Certificate: | Download |
| Author Reg. ID: |
IJRTI_210531
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| Published Paper Id: | IJRTI2604005 |
| Published In: | Volume 11 Issue 4, April-2026 |
| DOI: | https://doi.org/10.56975/ijrti.v11i4.210531 |
| Abstract: | The traditional architecture of System-on-Chip (SoC) has changed with the launch of chiplet-based architectures, enabling modular System-on-Chip integration and providing benefits in scalability, performance, and design flexibility. The review analyzes recent advances and the timing and power optimization problems of chiplet-based SoCs, particularly when heterogeneous interconnects are involved. Because chiplets may operate at different voltages, frequencies, and process nodes, timing synchronization and effective power distribution are essential. The article summarizes recent studies on modular AI acceleration, interconnect protocols, cost–performance trade-offs, and power management frameworks, with special emphasis on heterogeneous integration approaches such as 2.5D and 3D packaging. New tools and protocols, such as ChIP and decentralized power control mechanisms, are mentioned with respect to their role in reducing latency, energy consumption, and design complexity. Moreover, the article discusses developments in design automation and semiconductor technologies that support resilient timing closure and power optimization within multi-chiplet frameworks. The review indicates the significance of standardization, architectural co-design, and predictive EDA tools in realizing high-performance, energy-efficient chiplet-based SoCs suitable for next-generation computing systems. |
| Keywords: | chiplet-based SoC, timing optimization, power management, heterogeneous interconnects |
| Cite Article: | "Timing and Power Optimization in Chiplet-Based SoCs with Heterogeneous Interconnects", International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2456-3315, Vol.11, Issue 4, page no.a34-a39, April-2026, Available :http://www.ijrti.org/papers/IJRTI2604005.pdf |
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2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016 An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator |
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Published Paper ID: IJRTI2604005
Registration ID:210531
Published In: Volume 11 Issue 4, April-2026
DOI (Digital Object Identifier): https://doi.org/10.56975/ijrti.v11i4.210531
Page No: a34-a39 Country: -, -, India Research Area: Science & Technology Publisher : IJ Publication Published Paper URL : https://www.ijrti.org/viewpaperforall?paper=IJRTI2604005 Published Paper PDF: https://www.ijrti.org/papers/IJRTI2604005 |
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ISSN: 2456-3315
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Journal Starting Year (ESTD) : 2016
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