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Impact Factor : 8.14

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Paper Title: MFA Based RISC-V Evalution and strategy Exploration of MRAM
Authors Name: G. Sowjanya , M.Prabhakar , P.Chandrahasan Reddy , G.Jagan , T.Anil Kumar
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IJRTI_203086
Published Paper Id: IJRTI2505108
Published In: Volume 10 Issue 5, May-2025
DOI: https://doi.org/10.56975/ijrti.v10i5.203086
Abstract: Abstract:This project presents a 16-bit RISC processor designed with a Multiplier-Free Algorithm (MFA) to replace the conventional Full Adder (FA), thereby reducing power consumption, delay, and area utilization. The Reduced Instruction Set Computer (RISC) architecture offers enhanced performance, higher operational speed, and a simplified instruction set. The key achievement in this work is the implementation of MFA-based multipliers in the Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC), replacing traditional full-adder-based designs.MFA optimizes computational efficiency by eliminating complex multiplication operations, significantly improving processing speed and reducing overall power consumption. Additionally, the processor incorporates Magnetoresistive Random Access Memory (MRAM) for enhanced energy efficiency and non-volatile storage. The designed RISC processor consists of functional blocks such as a Control Unit, Data Path, Register Bank, Program Counter, and Memory Unit.The proposed MFA-based RISC processor is capable of executing 14 instructions efficiently. It exhibits power savings and reduced delay in In comparison with conventional MAC and ALU architectures, the incorporation of the Multi-Function ALU (MFA) within the Vedic ALU and MAC units significantly improves computational speed while effectively reducing power consumption and area utilization. This approach achieves approximately a 2.5% decrease in LUT (Look-Up Table) usage. The complete 16-bit RISC processor architecture, based on MFA, is implemented using Verilog HDL and synthesized using Xilinx Vivado 2018.3. Additionally, MRAM (Magneto resistive RAM) is designed using Tanner EDA tools and seamlessly integrated into the Vivado environment for evaluation as part of the RISC processor system.
Keywords: Keywords:- Reduced Instruction Set Computer; VonNeumann architecture; Verilog HDl, Vedic Mathematics, Urdhva-Tiryagbhyam Sutra
Cite Article: "MFA Based RISC-V Evalution and strategy Exploration of MRAM", International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2455-2631, Vol.10, Issue 5, page no.b45-b52, May-2025, Available :http://www.ijrti.org/papers/IJRTI2505108.pdf
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ISSN: 2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publication Details: Published Paper ID: IJRTI2505108
Registration ID:203086
Published In: Volume 10 Issue 5, May-2025
DOI (Digital Object Identifier): https://doi.org/10.56975/ijrti.v10i5.203086
Page No: b45-b52
Country: Kadapa, Andhra Pradesh, India
Research Area: Electronics & Communication Engg. 
Publisher : IJ Publication
Published Paper URL : https://www.ijrti.org/viewpaperforall?paper=IJRTI2505108
Published Paper PDF: https://www.ijrti.org/papers/IJRTI2505108
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ISSN: 2456-3315
Impact Factor: 8.14 and ISSN APPROVED, Journal Starting Year (ESTD) : 2016

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