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In Digital Signal Processing, Finite Impulse Response (FIR) filter is mostly used for communications and radar applications. The Performance of FIR filter depends on Multiplier and adder circuits used in filter. The key blocks of the filter are multipliers and adders, in which multiplier is the one which occupies the major silicon area and consumes more Area, Delay and Power. In this paper, we present a novel approximate computing scheme suitable for realizing the energy-efficient multiply-accumulate (MAC) processing. .First we design the approximate 4-2 compressors generating errors in the opposite direction while minimizing the computational costs. Based on the probabilistic analysis, positive and negative multipliers are then carefully developed to provide a similar error distance. Simulation results on various practical applications reveal that the proposed MAC processing offers the energy-efficient computing scenario by extending the range of approximate parts. The proposed FIR filter architecture with length of 6-tap are developed using Verilog HDL and Simulated by Modelsim 6.4c and Synthesized by Xilinx Tool. The Proposed Design is implemented using Spartan 3 XC 3S 200 PQ 208 Device
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"DESIGN OF POWER AND AREA EFFICIENT FIR FILTER USING APPROXIMATE MULTIPLIERS ", International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2455-2631, Vol.7, Issue 9, page no.111 - 126, September-2022, Available :http://www.ijrti.org/papers/IJRTI2209014.pdf
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2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator