Cyber security in Cloud system using VHDL based ASIC design of superscalar Homomorphic Encryption

Chandra kant Maurya , Abhishek Singh

Cloud System, FPGA, Homomorphic Encryption, VHDL, Cyber Security, Modulo Multiplier

Cyber Network Security and cryptography in high speed Cyber Networks demands for specific hardware in order to match up with fast cloud systems. In cryptographic module, Dual key Homomorphic, a symmetric key block cipher is been designed as algorithm for implementation. design goal is to increase data encryption rate i.e. throughput to a substantial value so that design may be used as a cryptographic processor in high speed Cyber Network applications. 2^n+1 modulo multiplier is a main element in Homomorphic encryption of cloud system, hence Paper work presented a new 2^n+1 modulo multiplier in design which generates less number of partial products (≤ n 2) and less area at very high speed. multiplication is based on Wallace tree along with specialized shifting. Presented work is mainly based on designing an optimized architecture for a cryptographic block and a Cyber Network intrusion detection system for a very high speed Cyber Network. All designs are coded using HDL language VHDL and are synthesized using Xilinx VIVADO 18.2i for verifying its functionality and working. Zynq-7000 pro FPGA is chosen as target platform device for realization of presented design.

Volume 6 Issue 2, February-2021

Pages : 1 - 8