ISSN2456-3315
Impact Factor10.57
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ESTD2016
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Paper Title
HYBRID CONFIGURABLE LOGIC ARCHITECTURE FOR FPGA’S
Authors
Y.Jeevan , Mr.I.Sharath Chandra , Prof. B. Kedarnath
Keywords
: FPGA, CLB’s, Look Up Tables, Multiplexers, Fracturable Architectures.
Abstract
In this paper, we have proposed a Hybrid configurable logic block architecture for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction. Technology mapping optimizations that target the proposed architectures are also implemented within ABC. Both accounting for complex logic block and routing area while maintaining mapping depth. For fracturable architectures, the proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
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How To Cite
"HYBRID CONFIGURABLE LOGIC ARCHITECTURE FOR FPGA’S", IJRTI - International Journal for Research Trends and Innovation (www.IJRTI.org), ISSN:2456-3315, Vol.2, Issue 7, page no.75 - 84, July-2017, Available :https://ijrti.org/papers/IJRTI1707014.pdf
Issue
Volume 2 Issue 7,
July-2017
Pages : 75 - 84
Other Publication Details
Paper Reg. ID: IJRTI_170422
Published Paper Id: IJRTI1707014
Downloads: 205,617
Research Area: Engineering
Country: Hyderabad, TELANGANA, India
Published Paper PDF: https://ijrti.org/papers/IJRTI1707014
Published Paper URL: https://ijrti.org/viewpaperforall?paper=IJRTI1707014
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ISSN: 2456-3315 | IMPACT FACTOR: 10.57 Calculated By Google Scholar | ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 10.57 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
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