An Implementation of Automatic Washing Machine Control System Using Verilog HDL

Gururaj E , Chetan B V

HDL, FPGA, Washing Machine Control System, Finite State Machine (FSM) model.

This paper proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the control system of an automatic washing machine. This paper accomplishes the above mentioned objective by implementing the Control System of an automatic washing using the Finite State Machine model. The Control System generates the control signals to control the overall operation of the washing machine. The Digital Design is simulated using Xilinx 14.1 ISE. The Verilog code for the Control System is then synthesized and implemented on Spartan 6 FPGA development board to verify its operation. This paper also demonstrates the reduction in Development Cycle by the use of Hardware Description Languages and FPGAs.

"An Implementation of Automatic Washing Machine Control System Using Verilog HDL", IJRTI - International Journal for Research Trends and Innovation (www.IJRTI.org), ISSN:2456-3315, Vol.2, Issue 7, page no.57 - 61, July-2017, Available :https://ijrti.org/papers/IJRTI1707011.pdf

Volume 2 Issue 7, July-2017

Pages : 57 - 61

Paper Reg. ID: IJRTI_170420

Published Paper Id: IJRTI1707011

Downloads: 205,642

Research Area: Engineering

Country: Davangere, Karnataka, India

Published Paper PDF: https://ijrti.org/papers/IJRTI1707011

Published Paper URL: https://ijrti.org/viewpaperforall?paper=IJRTI1707011

ISSN: 2456-3315 | IMPACT FACTOR: 10.57 Calculated By Google Scholar | ESTD YEAR: 2016

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 10.57 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

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Publisher: IJRTI (JW Publication)