Design and analysis of flip flop for low power VLSI applications - A Review
IJRTI1702003
Volume 2, Issue 2
Page 9 - 18
February 2017
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ISSN2456-3315
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Paper Title
Design and analysis of flip flop for low power VLSI applications - A Review
Authors
Yash Vardhan , Dhruv Nair , M. Vinoth Kumar
Keywords
Low Power Flip-Flop, Power Consumption, Area, Cost
Abstract
Technology and speed have always progressed hand in hand, from low scale integration to large and very large scale integration and from megahertz (MHz) to gigahertz (GHz). Similarly the system requirements are also rising up with this continuous advancement in process of technology and speed of operation. It is known that low power flipflops are crucial for the design of low-power digital systems. In this paper we analyse the details of various flip-flop design and optimization of various parameters. We have reviewed and studied lowest power flip-flops and compared their performances in the areas of Cost, Power consumption, Delay etc.
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IJRTI — journal style
"Design and analysis of flip flop for low power VLSI applications - A Review", IJRTI - International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2456-3315, Vol.2, Issue 2, page no.9 - 18, February-2017, Available :https://ijrti.org/papers/IJRTI1702003.pdf
APA — 7th edition
Vardhan, Y., Nair, D., & Kumar, M. V. (2017). Design and analysis of flip flop for low power VLSI applications - A Review. International Journal for Research Trends and Innovation, 2(2), 9 - 18. https://ijrti.org/viewpaperforall.php?paper=IJRTI1702003
MLA — 9th edition
Vardhan, Yash, et al. "Design and analysis of flip flop for low power VLSI applications - A Review." International Journal for Research Trends and Innovation, vol. 2, no. 2, 2017, pp. 9 - 18, https://ijrti.org/viewpaperforall.php?paper=IJRTI1702003.
Chicago — 17th, bibliography
Vardhan, Yash, Dhruv Nair, and M. Vinoth Kumar. "Design and analysis of flip flop for low power VLSI applications - A Review." International Journal for Research Trends and Innovation 2, no. 2 (2017): 9 - 18. https://ijrti.org/viewpaperforall.php?paper=IJRTI1702003.
Harvard — author–date
Vardhan, Y., Nair, D. and Kumar, M.V. (2017) 'Design and analysis of flip flop for low power VLSI applications - A Review', International Journal for Research Trends and Innovation, 2(2), pp. 9 - 18. Available at: https://ijrti.org/viewpaperforall.php?paper=IJRTI1702003
IEEE — numbered reference
Y. Vardhan, D. Nair and M. V. Kumar, "Design and analysis of flip flop for low power VLSI applications - A Review," IJRTI, vol. 2, no. 2, pp. 9 - 18, Feb. 2017.
Vancouver — biomedical
Vardhan Y, Nair D, Kumar MV. Design and analysis of flip flop for low power VLSI applications - A Review. IJRTI. 2017 Feb;2(2):9 - 18.
AMA — 11th edition
Vardhan Y, Nair D, Kumar MV. Design and analysis of flip flop for low power VLSI applications - A Review. IJRTI. 2017;2(2):9 - 18. Accessed at https://ijrti.org/viewpaperforall.php?paper=IJRTI1702003
BibTeX — Zotero, Mendeley, LaTeX
@article{IJRTI1702003,
author = {Yash Vardhan and Dhruv Nair and M. Vinoth Kumar},
title = {Design and analysis of flip flop for low power VLSI applications - A Review},
journal = {International Journal for Research Trends and Innovation},
volume = {2},
number = {2},
pages = {9 - 18},
year = {2017},
month = {February},
issn = {2456-3315},
url = {https://ijrti.org/viewpaperforall.php?paper=IJRTI1702003}
}
RIS — EndNote, RefWorks
TY - JOUR
AU - Vardhan, Yash
AU - Nair, Dhruv
AU - Kumar, M. Vinoth
TI - Design and analysis of flip flop for low power VLSI applications - A Review
T2 - International Journal for Research Trends and Innovation
JA - IJRTI
VL - 2
IS - 2
PY - 2017
SN - 2456-3315
UR - https://ijrti.org/viewpaperforall.php?paper=IJRTI1702003
SP - 9
EP - 18
ER -
International Journal for Research Trends and InnovationPublished by IJRTI (JW Publication)
2456-3315ISSN
10.57Impact Factor
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OpenAccess
Impact Factor 10.57 calculated by Google Scholar and Semantic Scholar.
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Declarations
Funding
No external funding was received for this study.
Conflict of Interest
The authors declare that they have no conflict of interest.
Acknowledgements
The authors would like to thank the reviewers and the editorial board of International Journal for Research Trends and Innovation for their careful reading and constructive comments, and all colleagues who supported the preparation of this manuscript.