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ISSN Approved Journal No: 2456-3315 | Impact factor: 8.14 | ESTD Year: 2016
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Impact Factor : 8.14

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Paper Title: Low Power Lector Based Frequency Divider in 45nm technology
Authors Name: Meghana R , Dr Kiran V
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Published Paper Id: IJRTI2210093
Published In: Volume 7 Issue 10, October-2022
Abstract: Deep submicron CMOS circuits are currently confronting a significant technological issue with power consumption. Because of the high transistor density, low voltage, and thinner oxide layer, leakage power considerably and quickly rises as process technology becomes more advanced. Sub-threshold leakage current increases in CMOS devices as channel length is scaled down. In this paper, three low-power architectures—LECTOR, GALEOR, and DRAIN GATING—are contrasted. This paper aims to give a thorough analysis and comparison of the above mentioned leakage power reduction techniques that have been used. The power consumption and propagation delay of the fundamental CMOS NAND gates using the low power techniques are compared. With no or little change in the critical route delay of the circuits as a whole, significant power savings are accomplished. A performance analysis is done on a D flip-flop that is made using the above mentioned low power techniques. It is found that LECTOR based low power technique is the most efficient architecture. A frequency divider circuit is built using the most efficient D-flip flop, which can split frequencies by 2, 4, and 8. Cadence Virtuoso is used for the design and analysis using 45nm technology.
Keywords: Cadence Virtuoso, 45nm, CMOS, NAND, D-flip flop, Low power, LECTOR based, GALEOR based, DRAIN GATING based, frequency divider, power, propagation delay
Cite Article: "Low Power Lector Based Frequency Divider in 45nm technology", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.7, Issue 10, page no.680 - 686, October-2022, Available :http://www.ijrti.org/papers/IJRTI2210093.pdf
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ISSN: 2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publication Details: Published Paper ID: IJRTI2210093
Registration ID:184438
Published In: Volume 7 Issue 10, October-2022
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Page No: 680 - 686
Country: BANGALORE, Karnataka, India
Research Area: Electronics & Communication Engg. 
Publisher : IJ Publication
Published Paper URL : https://www.ijrti.org/viewpaperforall?paper=IJRTI2210093
Published Paper PDF: https://www.ijrti.org/papers/IJRTI2210093
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ISSN: 2456-3315
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