IJRTI
International Journal for Research Trends and Innovation
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ISSN Approved Journal No: 2456-3315 | Impact factor: 8.14 | ESTD Year: 2016
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Impact Factor : 8.14

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Paper Title: Comparative Analysis of Efficient Designs of D-Latch using 32nm CMOS Technology
Authors Name: Lalitesh Singh , Surendra Bohra
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IJRTI_180249
Published Paper Id: IJRTI1806006
Published In: Volume 3 Issue 6, June-2018
DOI:
Abstract: In this paper we have proposed various efficient designs of low power D-latch using 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W/L ratio of each transistor in each circuit. We have taken power supply of 0.9V. We have calculated average power consumed propagation delay and power delay product.
Keywords: Latch, CMOS, Clock, Power Delay Product, MOSFET
Cite Article: "Comparative Analysis of Efficient Designs of D-Latch using 32nm CMOS Technology", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.3, Issue 6, page no.30 - 38, June-2018, Available :http://www.ijrti.org/papers/IJRTI1806006.pdf
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ISSN: 2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publication Details: Published Paper ID: IJRTI1806006
Registration ID:180249
Published In: Volume 3 Issue 6, June-2018
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Page No: 30 - 38
Country: Jaipur, Rajasthan, India
Research Area: Engineering
Publisher : IJ Publication
Published Paper URL : https://www.ijrti.org/viewpaperforall?paper=IJRTI1806006
Published Paper PDF: https://www.ijrti.org/papers/IJRTI1806006
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ISSN: 2456-3315
Impact Factor: 8.14 and ISSN APPROVED, Journal Starting Year (ESTD) : 2016

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