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In this paper we have proposed various efficient designs of low power D-latch using 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W/L ratio of each transistor in each circuit. We have taken power supply of 0.9V. We have calculated average power consumed propagation delay and power delay product.
Keywords:
Latch, CMOS, Clock, Power Delay Product, MOSFET
Cite Article:
"Comparative Analysis of Efficient Designs of D-Latch using 32nm CMOS Technology", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.3, Issue 6, page no.30 - 38, June-2018, Available :http://www.ijrti.org/papers/IJRTI1806006.pdf
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ISSN:
2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator