ugc approved journal list IJRTI Research Journal
International Journal for Research Trends and Innovation
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Issue: August 2018

Volume 3 | Issue 8

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Paper Title: Comparative Analysis of Efficient Designs of D-Latch using 32nm CMOS Technology
Authors Name: Lalitesh Singh , Surendra Bohra
Unique Id: IJRTI1806006
Published In: Volume 3 Issue 6, June-2018
Abstract: In this paper we have proposed various efficient designs of low power D-latch using 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W/L ratio of each transistor in each circuit. We have taken power supply of 0.9V. We have calculated average power consumed propagation delay and power delay product.
Keywords: Latch, CMOS, Clock, Power Delay Product, MOSFET
Cite Article: "Comparative Analysis of Efficient Designs of D-Latch using 32nm CMOS Technology", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.3, Issue 6, page no.30 - 38, June-2018, Available :http://www.ijrti.org/papers/IJRTI1806006.pdf
Downloads: 00038
Publication Details: Published Paper ID: IJRTI1806006
Registration ID:180249
Published In: Volume 3 Issue 6, June-2018
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ISSN Number: 2456 - 3315
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