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Volume 3 | Issue 4

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Paper Title: 64-Bit Radix_16 Booth Multiplier Using Partial Products
Authors Name: M.V.Akhil Kumar , M.Bharath Kumar , F.Antony Chethan , M.Rama Krishna
Unique Id: IJRTI1804006
Published In: Volume 3 Issue 4, April-2018
Abstract: In this paper, we describe an optimization for binary radix-16 (modified) Booth recoded multipliers to reduce the maximum height of the partial product columns to [n/4] for n = 64-bit unsigned operands. This is in contrast to the conventional maximum height of [(n + 1)/4].Therefore ,a reduction of one unit in the maximum height is achieved. This reduction may add flexibility during the design of the pipelined multiplier to meet the design goals, it may allow further optimizations of the partial product array reduction stage in terms of area/delay/power and/or may allow additional addends to be included in the partial product array without increasing the delay. The method can be extended to Booth recoded radix-8 multipliers, signed multipliers, combined signed/unsigned multipliers, and other values of n.
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Cite Article: "64-Bit Radix_16 Booth Multiplier Using Partial Products", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.3, Issue 4, page no.29 - 34, April-2018, Available :http://www.ijrti.org/papers/IJRTI1804006.pdf
Downloads: 00024
Publication Details: Published Paper ID: IJRTI1804006
Registration ID:180079
Published In: Volume 3 Issue 4, April-2018
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ISSN Number: 2456 - 3315
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