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Paper Title: A New Low Power High Speed Modified ONOFIC Approach in DSM Technology
Authors Name: Mridul Kumar , Mr. Suresh Sahadeorao Gawande
Unique Id: IJRTI1710012
Published In: Volume 2 Issue 10, October-2017
Abstract: Abstract:- Since the last two decades, the trend of device miniaturization has increased to get better performance with a smaller area of the logic functions. In deep submicron regime, the demand of fabrication of nanoscale Complementary metal oxide semiconductor (CMOS) VLSI circuits has increased due to evaluation of modern successful portable systems. Leakage power dissipation and reliability issues are major concerns in deep submicron regime for VLSI chip designers. Power supply voltage has been scaled down to maintain the performance yield in future deep submicron regime. The threshold voltage is the critical parameter to trade-of the performance yield and leakage power dissipation in nanoscaled devices. The simulation results on Synopsys HSPIC at 45nm and 32nm technology at 10 MHz frequency. Proposed leakage reduction technique provides 40% reduction in leakage over the existing leakage reduction technique in the literature.
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Cite Article: "A New Low Power High Speed Modified ONOFIC Approach in DSM Technology", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.2, Issue 10, page no.73 - 78, October-2017, Available :http://www.ijrti.org/papers/IJRTI1710012.pdf
Downloads: 00055
Publication Details: Published Paper ID: IJRTI1710012
Registration ID:170548
Published In: Volume 2 Issue 10, October-2017
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ISSN Number: 2456 - 3315
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