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Volume 3 | Issue 7

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Authors Name: Y.Jeevan , Mr.I.Sharath Chandra , Prof. B. Kedarnath
Unique Id: IJRTI1707014
Published In: Volume 2 Issue 7, July-2017
Abstract: In this paper, we have proposed a Hybrid configurable logic block architecture for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction. Technology mapping optimizations that target the proposed architectures are also implemented within ABC. Both accounting for complex logic block and routing area while maintaining mapping depth. For fracturable architectures, the proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
Keywords: : FPGA, CLB’s, Look Up Tables, Multiplexers, Fracturable Architectures.
Cite Article: "HYBRID CONFIGURABLE LOGIC ARCHITECTURE FOR FPGA’S", International Journal of Science & Engineering Development Research (, ISSN:2455-2631, Vol.2, Issue 7, page no.75 - 84, July-2017, Available :
Downloads: 000307
Publication Details: Published Paper ID: IJRTI1707014
Registration ID:170422
Published In: Volume 2 Issue 7, July-2017
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ISSN Number: 2456 - 3315
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