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Volume 2 | Issue 9

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Paper Title: An Implementation of Automatic Washing Machine Control System Using Verilog HDL
Authors Name: Gururaj E , Chetan B V
Unique Id: IJRTI1707011
Published In: Volume 2 Issue 7, July-2017
Abstract: This paper proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the control system of an automatic washing machine. This paper accomplishes the above mentioned objective by implementing the Control System of an automatic washing using the Finite State Machine model. The Control System generates the control signals to control the overall operation of the washing machine. The Digital Design is simulated using Xilinx 14.1 ISE. The Verilog code for the Control System is then synthesized and implemented on Spartan 6 FPGA development board to verify its operation. This paper also demonstrates the reduction in Development Cycle by the use of Hardware Description Languages and FPGAs.
Keywords: HDL, FPGA, Washing Machine Control System, Finite State Machine (FSM) model.
Cite Article: "An Implementation of Automatic Washing Machine Control System Using Verilog HDL", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.2, Issue 7, page no.57 - 61, July-2017, Available :http://www.ijrti.org/papers/IJRTI1707011.pdf
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Publication Details: Published Paper ID: IJRTI1707011
Registration ID:170420
Published In: Volume 2 Issue 7, July-2017
DOI (Digital Object Identifier):
ISSN Number: 2456 - 3315
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