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Volume 2 | Issue 10

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Paper Title: Reversible BCD Adder Emphatic Design and Exertion
Authors Name: P. Naga Santosh , G. Ramesh
Unique Id: IJRTI1704009
Published In: Volume 2 Issue 4, April-2017
Abstract: In the past few decades Reversible logic is one of the most significant research area Reversible logic allows low power dissipating circuit design and founds its applicat -ion in quantum computing, digital signal processing, crypt -ography and optical information processing.BCD adder is an essential component for processors and optimized design of these adders. In this paper an augment -ation method is proposed to realize a reversible Binary Coded Decimal adder using HNG, Fredkin,Feynman --and Peres gates. It had been evidence that the suggested design offers less hardware involvement. This recommended reversible BCD adder is evaluated and optimized in terms of quantum cost and gate count, result in high speed BCD adder with optimized area.
Keywords: Emphatic design , Garbage Output, Revesible Logic, Quantum Cost, Binary Coded Decimal Adder.
Cite Article: "Reversible BCD Adder Emphatic Design and Exertion", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.2, Issue 4, page no.29 - 33, April-2017, Available :http://www.ijrti.org/papers/IJRTI1704009.pdf
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Publication Details: Published Paper ID: IJRTI1704009
Registration ID:170108
Published In: Volume 2 Issue 4, April-2017
DOI (Digital Object Identifier):
ISSN Number: 2456 - 3315
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